Electrostatic discharge (ESD) refers to a phenomena wherein a charged device of a given potential suddenly discharges carriers to a separate device of lower potential. The discharge occurs over a short time frame and, therefore, results in a momentarily large current, if the resistance of the discharge path is kept low. The most common example of ESD occurs when a human walks over a carpeted area in low humidity, thereby collecting an electrostatic charge. If the charged human touches a semiconductor device, an electrostatic discharge takes place from the human to elements of the semiconductor device. Such discharges can damage the semiconductor device unless means are provided for clamping the large voltages and diverting the currents resulting from the electrostatic discharge.
FIG. 1 shows a prior art schematic diagram of a typical electrostatic discharge protection circuit for IC input pads. An input pad 101 is provided for interface with the internal circuit of the IC 103. Disposed between the input pad 101 and the internal circuit 103 are a pMOS 105 and an nMOS 107. The pMOS and nMOS devices have their gate electrodes connected to their sources. In general, for input pad protection, the junction breakdown voltages of the nMOS 107 and pMOS 105 should be smaller than the gate oxide breakdown voltage and higher than 1.1 V.sub.dd. However, as devices are miniaturized, the thickness of the gate oxide used in the MOSFET devices becomes smaller. The "snapback" effect becomes difficult to control for deep submicron technology. The snapback effect is detailed in U.S. Pat. No. 5,804,860 to Amerasekera.
Generally, an ESD pulse will generate a large amount of joule heating within the MOSFET devices. However, deep submicron devices utilize shallow junctions for better short channel effect control, which reduces the joule heating capability. Therefore, in order to reduce the maximum current density and provide a uniform current path, one prior art practice uses an ESD implant to broaden the source/drain profiles. Thus, as can be seen in FIG. 2, a conventional lightly doped drain MOSFET includes a gate 201, sidewall spacers 203, lightly doped drain regions 205, and source and drain implants 207 and 209, respectively. Additionally, an ESD implant 211 is used to broaden the source drain profiles. Typically, the ESD implant 211 is an implant having the same conductivity type of the source and drain, but of lower concentration. Therefore, the ESD implant 211 is a n-type implant and can be, for example, formed by phosphorous implants. Furthermore, although an nMOS device is shown in FIG. 2, a pMOS transistor can be easily formed by reversing the implant types. A more detailed discussion of this prior art may be found in A. Amerasekera and C. Duvvury, "ESD in Silicon Integrated Circuits," John Wiley and Sons, Inc. (1996), at page 180.
Nevertheless, the prior art still does not provide adequate control of snapback trigger voltage. The present invention addresses this problem.